March 14-15, 2021
Virtual
CSTIC 2021 is one of the largest and the most comprehensive annual semiconductor technology conferences in China and Asia since 2000. Organized by SEMI, IMEC and IEEE-EDS, co-organized by IMECAS. CSTIC 2021 will be held on March 14-15, 2021 in Shanghai, China, in conjunction with SEMICON China 2021. Virtual conference will be held on March 14-April 11 at SEMI Cloud. The conference will have nine symposiums covering all aspects of semiconductor technology with focus on manufacturing and advanced technology, including detailed manufacturing processes, device design, integration, materials, and equipment, as well as emerging semiconductor technologies, circuit design, and silicon material applications. Hot topics, such as artificial intelligence (AI) chips, 6G chips, neuromorphic computing technology, advanced memory technology, 3D integration, MEMS technology will also be addressed in the conference.
Runhui Huang, Xing-fu Zhong, Gu Xu, Boyu Zhang, Jakub Koza, Sean Simmons will be presenting their research, Development of planarizing spin-on carbon material for high-temperature processes
Wenkai Cheng will be presenting their research, A Novel Multifunctional Single-Layer Adhesive Used for both Temporary Bonding and Mechanical Debonding in Wafer-Level Packaging Applications
Development of planarizing spin-on carbon material for high-temperature processes abstract:
For the last several advanced semiconductor nodes, as the industry moves towards 7- and 5-nm processes, the requirements for patterning and image transfer have increased dramatically. Multilayer material stacks are needed to pattern complex high-resolution structures. For carbon films, one key point is the tradeoff between planarization and high-temperature stability requirements used in patterning and post-patterning process integration. On one side, the need for thermally stable carbon materials is steadily increasing, for better pattern transfer fidelity (less line wiggling), chemical vapor deposition (CVD) compatibility where a plasma-enhanced CVD (PECVD) inorganic hardmask is deposited on top, and for the use as mandrels for pattern multiplication. On the other hand, due to the increased complexity of chip designs, gap filling and planarization of the underlying topography is also strongly desired. In addition, wet chemical resistance and the capability to be polished by chemical mechanical planarization (CMP) processes are often necessary. Design of a spin-on carbon (SOC) film to meet all the desired, but sometimes conflicting, properties using organic polymers with good solubility in fab-approved solvent systems requires innovative chemical design and rigorous experiment and tuning processes.
Brewer Science’s advanced material development is bringing forth low-shrinkage, high-temperature-stable SOCs with spin-bowl/drain compatibility for advanced node manufacturing and integration. The materials presented in this paper are stable up to 500-550°C with no weight loss, soluble in the solvents commonly used in semiconductor industry, can fill <10 nm narrow gaps, and have excellent planarization properties over a long distance. The coated film has very low thickness shrinkage during the bake conditions on the track and is stable through the subsequent high temperature PECVD process. The resulted dense carbon film provides extremely good planarization both locally and globally across the wafer. It demonstrated great chemical resistance to SC1 condition and can be CMP polished using commercially available slurries, if needed. During etch transfer, it showed very little after-develop inspection (ADI) and after-etch inspection (AEI) bias and maintained excellent line-width resolution through various critical dimensions. Moreover, this material’s good solubility allows it to be formulated with high solid content for >2 µm thickness, which has showed early promising results in filling some very-high-aspect-ratio gaps in certain memory applications.
Keywords: Multilayer lithography, spin on carbon, high temperature, planarization, SC1 resistance
A Novel Multifunctional Single-Layer Adhesive Used for both Temporary Bonding and Mechanical Debonding in Wafer-Level Packaging Applications abstract:
Temporary bonding (TB) and debonding (DB) of wafers have been widely developed and applied over the last decade in various wafer-level packaging technologies, such as package-on-package (PoP), fan-out integration, and 2.5D and 3D integration using through-silicon vias (TSVs). The materials used to achieve TB and DB are extremely critical and the industry’s current best practice is the use of two layers of materials (bonding layer and release layer). In this paper, a novel single-layer adhesive is presented to possess both functions of TB with mechanical DB. The properties of this material empower the capabilities of handling ultrathin wafers, supporting very low warpage for high-stress substrates, and surviving high-temperature processing. Testing on a blank silicon wafer thinned down to 20 µm showed neither defects nor edge chipping. In addition, a thermal simulation of 250°C for 30 minutes also passed qualification. Less than 30 µm warpage on an 8” wafer was also observed, which proves the material is friendly to high-stress substrates. More importantly, using fewer layers means fewer total processes, fewer cleaning steps, and lower cost of ownership.
Keywords: temporary bonding; mechanical debonding; wafer-level packaging; single-layer adhesive
