October 24-26, 2017
San Jose, CA
October 24-26, 2017
San Jose, CA
Double Tree by Hilton San Jose
Attend our presentation at Wafer Level Packaging (WLP) Processes Session 4
The Dual-layer Bonding Platform as A Technical Enabler for Wafer-Level Packaging Applications
Tuesday, October 24, 2017, 1:00-3:00 pm (Oak)
Xiao Liu, Ph.D., Brewer Science Inc
Author(s): Xiao Liu, Qi Wu, Dongshun Bai, Rama Puligadda, Tony Flaim
Wafer-level packaging has been widely adopted in large-scale production as a result of the market need for thinner, higher performing, smaller form-factor devices. These demands are driven largely by mobile, however as the technology progresses, other industry drivers are coming forth. A simplified bond and debond process that enables device manufacturers to meet higher temperature process requirements with simpler handling will help guide the industry into further adoption of these wafer-level packaging technologies.
Program: http://www.iwlpc.com/IWLPC-2017-Program.pdf?v=170918020906
About IWLPC:
IWLPC brings together the semiconductor industry’s most respected authorities to address all aspects of wafer-level, 3D device packaging, advanced manufacturing & test technologies.
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