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October 15, 2016 Blogs
Thermally curable middle layer for 193-nm trilayer resist process

New lithographic compositions, for use as middle layers in trilayer processes  resist processes can be applied as very thin films with a very thin layer of photoresist being applied to…

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October 15, 2016 Blogs
High-k metal gate (HKMG) technology for CMOS devices

High-k metal gate (HKMG) technology has become one of the front-runners for the next generation of CMOS devices. This new technology incorporates a high-k dielectric, which reduces leakage and improves…

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October 15, 2016 Blogs
Controlling the spin bowl environment to optimize spin coat quality

A variety of factors can affect the coat quality when spin processing. This article will focus on the role that the bowl environment, and in particlar the ability to control…

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October 15, 2016 Blogs
Bake plate enhancements for optimal thick-film curing results

High-uniformity bake plates have been displacing convection ovens for well over two decades in the microelectronics industry. The disadvantages of variable temperature zones, lengthened cure times, and considerable particle contamination…

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October 15, 2016 Blogs
Processing wafers with high-topography 3-D structures

Over the past decade, Brewer Science has developed and published various methods of creating a planar surface over three-dimensional (3-D) structures. Sharing these results invariably leads to a potential customer…

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October 15, 2016 Blogs
Jim Lamb at Science Cafe

At the Science Café event held at Farmers Gastropub on April 19, James E. (Jim) Lamb III, Brewer Science Corporate Technology Strategist and Director of the Printed Electronics Technology Center,…

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October 15, 2016 Blogs
Background of multilayer processing

As semiconductor devices evolve, smaller and smaller feature sizes are required to achieve the performance desired by the consumer. Smaller features give rise to lower power consumption for mobile devices,…

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